`timescale 1ns / 1ps
 
module ALU(X,Y,Aluc,Cout,Z);
 
    //00+ 01- 10& 11|
 
    input [31:0]X,Y;
 
    input [1:0]Aluc;
 
    output [31:0]Cout;
 
    output Z;
 
   
 
    wire[31:0]out_as,out_and,out_or,out_and_or;
 
   
 
    ADDSUB_32 as(X,Y,Aluc[0],out_as);
 
   
 
    assign out_and=X&Y;
 
    assign out_or=X|Y;
 
   
 
    MUX2X32 and_or_select(out_and,out_or,Aluc[0],out_and_or);//0& 1|
 
    MUX2X32 as_ao_selete(out_as,out_and_or,Aluc[1],Cout);//0+- 1&|
 
   
 
    assign Z=~|Cout;
 
endmodule